p1145-3s, p1145-hc cmos series full size (14 pin dip) metal clock oscillator p1145-3s: cmos with enable/ disable, p1145-hc without e/d lower ringing noise option available to reduce emi available in thru-hole or surface mount configuration 650 khz ? 69.999 mhz standard specifications overall frequency stability 50 ppm, 25 ppm, 20 ppm over operating temperature range operating temperature range 0 to +70 c is standard, but can be extended to - 40 to +85 c for certain frequencies supply voltage (vcc) 5.0 volts and 3.3 volts available symmetry (duty cycle) 40/60 to 60/40% is standard, but 45/55% at 50% of vcc is als o available (see waveform 1) output load -3s: enable/disable option (e/d) output enabled when pin #1 is open or at logic ? 1 ? ; output disabled when pin #1 is at logic ? 0 ? . rise and fall time frequency range (mhz) typical maximum 0.650 ? 10.000 7 10 3.0 4.0 10.001 ? 25.999 10 20 2.5 3.5 26.000 ? 34.999 15 25 2.5 3.5 35.000 ? 50.000 20 30 2.5 3.5 part numbering guide model frequency stability 45 = 50 ppm 44 = 25 ppm frequency in mhz special specifications (choose all that apply) p11 45 - 3s v - 60.0m - 30 - smd - xxx (internal code or blank) consult factory for available frequencies and specs. not all options available for all frequencies. a special part numbe r may be assigned. blank: std specs (5.0v 10% , 0 to +70 c, 40/60% sym) e: extended operating temperature range (- 40 to +85 c) n: lower ringing noise s: 45/55% symmetry at 50% of vcc v: supply voltage of 3.3 volts 10% 50.001 ? 69.999 25 35 2.5 3.5 frequency stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration a nd load surface mount option mechanical: not to scale inches (mm) surface mount (425) 776 - 1880, fax: (425) 776 - 2760, ple - sales@pletronics.com, www.pletronics.com 16 jun 2004 solder pad layout may use any combination of pins 1, 7, 8 & 14 shown. recommended pad size is .12 (3.1) x .07 (1.8) typical. pl tronics, inc. 0.807 (20.5) max pletronics 0.500 (12.7) max 0 .247 (6.28) max 0 .200 (5.08) max 0.600 (15.24) 0.300 (7.62) 1 7 14 8 -3s pin 1 = e/d -hc pin 1 = n.c. vcc out gnd 0.031 (0.8) 0.560 (14.23) max 0.300 (7.62) 0.200 (5.08) typ 1 1 1 14 14 14 8 8 8 7 7 7 0.250 (6.35) max 0.020 (.51) 0.820 (20.84) max 0.767 (19.49) 0.600 (15.24) standard load is 15pf (typ. 1 asic) maximum, see test circui t 3 or 1 (consult factory for heavier loads) tr & tf (ns) w/ 15pf load packaging tube or on pads, smd: bulk solder pad layout may use any combination of pins 1, 7, 8 & 14 shown. recommended pad size is .12 (3.1) x .07 (1.8) typical. 0.807 (20.5) max 0.500 (12.7) max 0 .247 (6.28) max 0 .200 (5.08) max 0.600 (15.24) 0.300 (7.62) 1 7 14 8 0.031 (0.8) 0.560 (14.23) max 0.300 (7.62) 0.200 (5.08) typ 1 1 1 14 14 14 8 8 8 7 7 7 0.250 (6.35) max 0.020 (.51) 0.820 (20.84) max 0.767 (19.49) 0.600 (15.24) due to part size and factory abilities, part marking may var y from lot to lot and may contain our part number or an inte rnal code. non-std output load: blank = 15 pf max, 30 = 30 pf max logic levels logic ? 1 ? 90% of vcc min; logic ? 0 ? 10% of vcc max 20 = 20 ppm pl tronics , inc. 19013 36th ave. w, suite h lynnwood, wa 98036 usa manufacturer of high quality frequency control products . -3s with e/d -hc no e/d series portions of the part number that appear after the frequency may not be marked on part (c of c provided) max. supply current icc (ma) w/ 15pf load 3.3v 5.0v due to part size and factory abilities, part marking may var y from lot to lot and may contain our part number or an internal code. thru hole - smd ringing noise depends on frequency and output load. see emi application no te cmos < 80 mhz page 11a - 16 ple p3sxesv 30.000m yywwxx ple p11xx-3sesv 30.000m yywwxx marking examples and explanation ple = pletronics sq3 = model code x = frequency stability esv = applicable specs (some internal) frequency in mhz ywwx = date code new old 1 e/d 7 gnd 8 out 14 vcc pin signal
|
